High-performance computing (HPC) performed on large sparse matrices has become an increasingly important area of computing. Field programmable gate arrays (FPGAs) are computer processing circuits that include configurable logical blocks, data interconnects, and other programmable digital logic resources. FPGAs may be used to accelerate sparse matrix processing as compared to traditional central processing units (CPUs) and/or graphics processing units (GPUs). FPGA designs may be manually selected to accelerate frequently used sparse kernels such as sparse matrix vector multiply (SpMV), triangular solvers, or other kernels. FPGA accelerators may only exist for well-understood sparse kernels. Additionally, manually designed FPGA accelerators may not consider the context of when the kernel is invoked.